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ISL6161
Data Sheet October 2, 2008 FN9104.4
Dual Power Distribution Controller
The ISL6161 is a HOT SWAP dual supply power distribution controller that can be used in PCI-Express applications. Two external N-Channel MOSFETs are driven to distribute and control power while providing load fault isolation. At turn-on, the gate of each external N-Channel MOSFET is charged with a 10A current source. Capacitors on each gate (see the "Typical Application Diagram" on page 1), create a programmable ramp (soft turn-on) to control in-rush currents. A built-in charge pump supplies the gate drive for the 12V supply N-Channel MOSFET switch. Overcurrent protection is facilitated by two external current sense resistors and FETs. When the current through either resistor exceeds the user programmed value, the controller enters the current regulation mode. The time-out capacitor, CTIM, starts charging as the controller enters the time-out period. Once CTIM charges to a 2V threshold, both the N-Channel MOSFETs are latched off. In the event of a hard and fast fault of at least 3x the programmed current limit level, the N-Channel MOSFET gates are pulled low immediately before entering the time-out period. The controller is reset by a rising edge on the ENABLE pin. The ISL6161 constantly monitors both output voltages and reports either one being low on the PGOOD output as a low. The 12V PGOOD Vth is ~10.8V and the 3.3V Vth is ~2.8V nominally.
Features
* HOT SWAP Dual Power Distribution and Control for +12V and +3.3V * Provides Fault Isolation * Programmable Current Regulation Level * Programmable Time-Out * Charge Pump Allows the Use of N-Channel MOSFETs * Power-Good and Overcurrent Latch Indicators * Adjustable Turn-On Ramp * Protection During Turn-On * Two Levels of Current Limit Detection Provide Fast Response to Varying Fault Conditions * 1s Response Time to Dead Short * 3s Response Time to 200% Current Overshoot * Pb-Free Available (RoHS compliant)
Applications
* PCI-Express Applications * Power Distribution and Control * Hot Plug, Hot Swap Components
Ordering Information
PART NUMBER ISL6161IBZA* (Note) ISL6161CB* PART MARKING ISL6161 IBZ ISL6161CB TEMP. RANGE (C) -40 to +85 0 to +70 0 to +70 PACKAGE 14 Ld SOIC (Pb-free) 14 Ld SOIC 14 Ld SOIC (Pb-free) PKG. DWG. # M14.15 M14.15 M14.15
Pinout
ISL6161 (14 LD SOIC) TOP VIEW
12VS 12VG VDD NC ENABLE 3VG 3VS 1 2 3 4 5 6 7 14 12VISEN 13 RILIM 12 GND 11 CPUMP 10 CTIM 9 8 PGOOD 3VISEN
ISL6161CBZA* 6161CBZ (Note)
*Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020
Typical Application Diagram
CPUMP RSENSE 12V OPTIONAL VDDRFILTER CFILTER 3.3V CGATE CGATE ENABLE INPUT ISL6161 12VS 12VISEN RILIM 12VG GND VDD CPUMP ENABLE CTIM 3VG PGOOD 3ISEN 3VS RSENSE RLOAD RILIM
CTIM 3.3V RLOAD
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2004, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
Simplified Schematic
12VIN
RSENSE
TO LOAD
12VS
OC
CLIM + -
R 100A 2R
12V
12ISEN
10A
2
12VG FALLING EDGE DELAY 18V CGATE OPTIONAL VDD RFILTER CFILTER NC RISING EDGE RESET VDD R QN R Q S ENABLE 12V CGATE 10A 3VG ENABLE FALLING EDGE DELAY 3VS 5VIN
FN9104.4 October 2, 2008
+ 3X
RILIM RILIM
ENABLE
18V
POR
GND
ENABLE
QPUMP
ISL6161
12V 10A 12V 3X + CLIM + OC R PGOOD 2R + 2V
CPUMP
CPUMP
TO VDD
CTIM CTIM + PGOOD OC LATCH
3ISEN ISL6161
OPTIONAL
RSENSE
TO LOAD
ISL6161 Pin Descriptions
PIN NUMBER SYMBOL 1 12VS FUNCTION 12V Source DESCRIPTION Connect to source of associated external N-Channel MOSFET switch to sense output voltage. Connect to the gate of associated N-Channel MOSFET switch. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to ~17.4V by a 10A current source. Connect to 12V supply. This can be either connected directly to the +12V rail supplying the load voltage or to a dedicated VDD +12V supply. If the former is chosen, special attention to VDD decoupling must be paid to prevent sagging as heavy loads are switched on.
2
12VG
12V Gate
3
VDD
Chip Supply
4 5
NC ENABLE
Not Connected Enable/Reset ENABLE is used to turn-on and reset the chip. Both outputs turn-on when this pin is driven low. After a current limit time-out, the chip is reset by the rising edge of a reset signal applied to the ENABLE pin. This input has 100A pull-up capability, which is compatible with 3V and 5V open drain and standard logic. Connect to the gate of the external 3V N-Channel MOSFET. A capacitor from this node to ground sets the turn-on ramp. At turn-on, this capacitor will be charged to ~11.4V by a 10A current source. Connect to the source side of 3V external N-Channel MOSFET switch to sense output voltage. Connect to the load side of the 3V sense resistor to measure the voltage drop across this resistor between 3VS and 3VISEN pins.
6
3VG
3V Gate
7
3VS
3 Source
8
3VISEN
3V Current Sense
9
PGOOD
Power-Good indicator Indicates that all output voltages are within specification. PGOOD is driven by an open drain N-Channel MOSFET. It is pulled low when any output is not within specification. Current Limit Timing Capacitor Connect a capacitor from this pin to ground. This capacitor controls the time between the onset of current limit and chip shutdown (current limit time-out). The duration of current limit time-out (in seconds) = 200k x CTIM (Farads). Connect a 0.1F capacitor between this pin and VDD (pin 3). Provides charge storage for 12VG drive.
10
CTIM
11
CPUMP GND RILIM
Charge Pump Capacitor Chip Ground Current Limit Set Resistor
12 13
A resistor connected between this pin and ground determines the current level at which current limit is activated. This current is determined by the ratio of the RILIM resistor to the sense resistor (RSENSE). The current at current limit onset is equal to 10A x (RILIM/RSENSE). The ISL6161 is limited to a 10k min. value (OC Vth = 100mV) resistor whereas the ISL6161 can accommodate a 5k resistor for a lower OC Vth (50mV). Connect to the load side of sense resistor to measure the voltage drop across this resistor.
14
12VISEN 12V Current Sense
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FN9104.4 October 2, 2008
ISL6161
Absolute Maximum Ratings TA = +25C
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V 12VG, CPUMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 21V 12VISEN, 12VS . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to VDD + 0.3V 3VISEN, 3VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to 7.5V PGOOD, RILIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.5V ENABLE, CTIM, 3VG . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (Class 2)
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . +10.5V to +13.2V Temperature Range (TA) ISL6161IB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C ISL6161CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
VDD = 12V, CVG = 0.01F, CTIM = 0.1F, RSENSE = 0.1, CBULK = 220F, ESR = 0.5, TA = TJ = -40C to +85C, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER 12V CONTROL SECTION Current Limit Threshold Voltage (Voltage Across Sense Resistor) 3x Current Limit Threshold Voltage (Voltage Across Sense Resistor) 20% Current Limit Response Time (Current within 20% of Regulated Value) 10% Current Limit Response Time (Current within 10% of Regulated Value) 1% Current Limit Response Time (Current within 1% of Regulated Value) Response Time to Dead Short Gate Turn-On Time Gate Turn-On Current 3x Gate Discharge Current 12V Undervoltage Threshold Charge Pumped 12VG Voltage 3.3V CONTROL SECTION Current Limit Threshold Voltage (Voltage Across Sense Resistor) 3x Current Limit Threshold Voltage (Voltage Across Sense Resistor) 20% Current Limit Response Time (Current within 20% of Regulated Value) 10% Current Limit Response Time (Current within 10% of Regulated Value)
VIL12V
RILIM = 10k RILIM = 5k
92 47 250 100 8 10.5
100 53 300 165 2 4 10 500 12 10 0.75 10.8 17.3
108 59 350 210 12 11.0 17.9
mV mV mV mV s s s ns ms A A V V
3 x VIL12V
RILIM = 10k RILIM = 5k
20%iLrt 10%iLrt 1%iLrt RTSHORT tON12V ION12V 3XdisI 12VVUV V12VG
200% Current Overload, RILIM = 10k, RSHORT = 6.0 200% Current Overload, RILIM = 10k, RSHORT = 6.0 200% Current Overload, RILIM = 10k, RSHORT = 6.0 C12VG = 0.01F C12VG = 0.01F C12VG = 0.01F 12VG = 18V
CPUMP = 0.1F
16.8
VIL3V
RILIM = 10k RILIM = 5k
92 47 250 100 -
100 53 300 155 2 4
108 59 350 210 -
mV mV mV mV s s
3 x VIL3V
RILIM = 10k RILIM = 5k 200% Current Overload, RILIM = 10k, RSHORT = 2.5 200% Current Overload, RILIM = 10k, RSHORT = 2.5
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FN9104.4 October 2, 2008
ISL6161
Electrical Specifications
VDD = 12V, CVG = 0.01F, CTIM = 0.1F, RSENSE = 0.1, CBULK = 220F, ESR = 0.5, TA = TJ = -40C to +85C, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL TEST CONDITIONS 200% Current Overload, RILIM = 10k, RSHORT = 2.5 RTSHORT tON3V ION3V 3xdisI 3.3VVUV 3VG CVG = 0.01F CVG = 0.01F CVG = 0.01F CVG = 0.01F, ENABLE = Low 2.7 11.2 MIN 8 TYP 10 500 5 10 0.75 2.85 11.9 12 3.0 MAX UNITS s ns ms A A V V
PARAMETER 1% Current Limit Response Time (Current within 1% of Regulated Value) Response Time To Dead Short Gate Turn-On Time Gate Turn-On Current 3x Gate Discharge Current 3.3V Undervoltage Threshold 3.3VG High Voltage
SUPPLY CURRENT AND IO SPECIFICATIONS VDD Supply Current VDD POR Rising Threshold VDD POR Falling Threshold Current Limit Time-Out ENABLE Pull-up Voltage ENABLE Rising Threshold ENABLE Hysteresis ENABLE Pull-Up Current Current Limit Time-Out Threshold (CTIM) CTIM Charging Current CTIM Discharge Current CTIM Pull-Up Current RILIM Pin Current Source Output Charge Pump Output Current Charge Pump Output Voltage Charge Pump Output Voltage - Loaded Charge Pump POR Rising Threshold Charge Pump POR Falling Threshold tILIM PWRN_V PWR_Vth PWR_hys PWRN_I CTIM_Vth CTIM_I CTIM_disI CTIM_disI RILIM_Io Qpmp_Io Qpmp_Vo Qpmp_VIo Qpmp + Vth Qpmp - Vth CPUMP = 0.1F, CPUMP = 16V No load Load current = 100A VCTIM = 8V CTIM = 0.1F ENABLE pin open IVDD 4 9.5 9.0 1.8 1.1 0.1 60 1.8 8 1.7 3.5 90 320 17.2 16.2 15.6 15.2 8 10.0 9.4 20 2.4 1.5 0.2 80 2 10 2.6 5 100 560 17.4 16.7 16 15.7 10 10.7 9.8 3.2 2 0.3 100 2.2 12 3.5 6.5 110 900 16.5 16.2 mA V V ms V V V A V A mA mA A A V V V V
ISL6161 Description and Operation
The ISL6161 is a multi-featured +12V and +3.3V dual power supply distribution controller. Its features include programmable current regulation (CR) limiting and time to latch off. At turn-on, the gate capacitor of each external N-Channel MOSFET is charged with a 10A current source. These capacitors create a programmable ramp (soft turn-on). A charge pump supplies the gate drive for the 12V supply control FET switch driving that gate to 17V. The load currents pass through two external current sense resistors. When the voltage across either resistor quickly exceeds the user programmed Current Regulation voltage threshold (CRVth) level, the controller enters current regulation. The CRVth is set by the external resistor value on RILIM pin. At
this time, the time-out capacitor, CTIM, starts charging with a 10A current source and the controller enters the time-out period. The length of the time-out period is set by the single external capacitor (see Table 2) placed from the CTIM pin (pin 10) to ground and is characterized by a lowered gate drive voltage to the appropriate external N-Channel MOSFET. Once CTIM charges to 2V, an internal comparator is tripped resulting in both N-Channel MOSFETs being latched off. If the voltage across the sense resistors rises slowly in response to an OC condition, then the CR mode is entered at ~95% of the programmed CR level. This difference is due to the necessary hysteresis and response time in the CR control circuitry. Table 1 shows RSENSE and RILIM recommendations and resulting CR level for the PCI-Express add-in card connector sizes specified.
5
FN9104.4 October 2, 2008
ISL6161
.
TABLE 1. RSENSE AND RILIM RECOMMENDATIONS PCI-EXPRESS ADD-IN CARD CONNECTOR X1 3.3V RSENSE 12V RSENSE NOMINAL (m), (m), CRVth NOMINAL NOMINAL RILIM (mV) CR (A) CR (A) (k) 10 4.99 X4/X8 10 4.99 X16 10 4.99 30, 3.3 15, 3.5 30, 3.3 15, 3.5 30, 3.3 15, 3.5 150, 0.7 90, 0.6 40, 2.5 20, 2.6 16, 6.3 8, 6.6 100 53 100 53 100 53
ISL6161 Application Considerations
In a non PCI-Express, motor drive application, Current loop stabilization is facilitated through a small value resistor in series with the gate timing capacitor. As the ISL6161 drives a highly inductive current load, instability characterized by the gate voltage repeatedly ramping up and down may appear. A simple method to enhance stability is provided by the substitution of a larger value gate resistor. Typically, this situation can be avoided by eliminating long point-to-point wiring to the load. With the ENABLE internal pull-up, the ISL6161 is well suited for implementation on either side of the connector where a motherboard prebiased condition or a load board staggered connection is present. In either case, the ISL6161 turns on in a soft-start mode protecting the supply rail from sudden current loading. During the Time-Out delay period with the ISL6161 in current limit mode, the VGS of the external N-Channel MOSFETs is reduced driving the N-Channel MOSFET switch into a high rDS(ON) state. Thus, avoid extended time-out periods as the external N-Channel MOSFETs may be damaged or destroyed due to excessive internal power dissipation. Refer to the MOSFET manufacturers data sheet for SOA information. With the high levels of in-rush current e.g., highly capacitive loads and motor start-up currents, choosing the current regulation (CR) level is crucial to provide both protection and still allow for this in-rush current without latching off. Consider this in addition to the time-out delay when choosing MOSFETs for your design. Physical layout of RSENSE resistors is critical to avoid inadvertently lowering the CR and trip levels. Ideally, trace routing between the RSENSE resistors and the ISL6161 should be as direct and as short as possible with zero current in the sense lines.
CORRECT INCORRECT
NOTE: Nominal CR Vth = RILIM x 10A. TABLE 2. CTIM CAPACITOR (F) 0.022 0.047 0.1 NOMINAL TIME-OUT PERIOD (ms) 4.4 9.4 20
NOTE: Nominal time-out period in seconds = CTIM x 200k.
The ISL6161 responds to a load short (defined as a current level 3x the OC set point with a fast transition) by immediately driving the relevant N-Channel MOSFET gate to 0V in ~3s. The gate voltage is then slowly ramped up, soft-starting the N-Channel MOSFET to the programmed current regulation limit level. This is the start of the time-out period if the abnormal load condition still exists. The programmed current regulation level is held until either the OC event passes or the time-out period expires. If the former is the case, then the N-Channel MOSFET is fully enhanced and the CTIM charging current is diverted away from the capacitor. If the time-out period expires prior to OC resolution, then both gates are quickly pulled to 0V turning off both N-Channel MOSFETs simultaneously. Upon any UV condition, the PGOOD signal will pull low when tied high through a resistor to the logic supply. This pin is a fault indicator but not the OC latch-off indicator. For an OC latch-off indication, monitor CTIM, pin 10. This pin will rise rapidly to 12V once the time-out period expires. See "Simplified Schematic" on page 2 for OC latch-off circuit suggestion. The ISL6161 is reset by a rising edge on the ENABLE pin and is turned on by the ENABLE pin being driven low.
TO ISEN AND RISET
CURRENT SENSE RESISTOR
FIGURE 1. SENSE RESISTOR PCB LAYOUT
6
FN9104.4 October 2, 2008
ISL6161
Open load detection can be accomplished by monitoring the ISEN pins. Although gated off, the external FET IDSS will cause the ISEN pin to float above ground to some voltage when there is no attached load. If this is not desired, 5k resistors from the xISEN pins to ground will prevent the outputs from floating when the external switch FETs are disabled and the outputs are open. For PCI-Express applications, the ISL6161 and the ISL6118 provide the fundamental hotswap function for the +12V and +3.3V main rails and the +3.3V aux respectively, as shown in the "PCI-Express Implementation of ISL6161 and ISL6118" on page 10.
Typical Performance Curves
8.4 8.2 SUPPLY CURRENT (mA) 8.0 7.8 7.6 7.4 7.2 -40 102 -40 CURRENT (A) 105
104
103
-30
-20 -10
0
10
20
30
40
50
60
70
80
-30
-20
-10
0
10
20
30
40
50
60
70
80
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 2. SUPPLY CURRENT
FIGURE 3. RILIM SOURCE CURRENT
10.7 CTIM OC VOLTAGE THRESHOLD (V) -30 -20 -10 0 10 20 30 40 TEMPERATURE (C) 50 60 70 80 CTIM CURRENT SOURCE (A)
2.04
2.02
10.6
2.00
10.5
1.98
10.4
1.96
10.3 -40
1.94 -40
-30 -20 -10
0 10 20 30 40 TEMPERATURE (C)
50
60
70
80
FIGURE 4. CTIM CURRENT SOURCE
FIGURE 5. CTIM OC VOLTAGE THRESHOLD
7
FN9104.4 October 2, 2008
ISL6161 Typical Performance Curves
10.920
(Continued)
2.8750
3.3V UV THRESHOLD (V)
12V UV THRESHOLD (V)
2.8725
10.902
2.8700
10.886
2.8675
10.870 -40
-20
0
20
40
60
80
2.8650 -40
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 6. 12V UV THRESHOLD
FIGURE 7. 3.3V UV THRESHOLD
17.36
11.935 11.930
17.6
17.34 12V GATE DRIVE (V) VOLTAGE (V) 12V VG 17.32 11.925 11.920 11.915 3.3VG 17.28 11.905 17.26 -40 11.900 80 11.910 3.3V GATE DRIVE (V)
17.4 CHARGE PUMP VOLTAGE NO LOAD 17.2
17.30
17.0 CHARGE PUMP VOLTAGE 100A LOAD
16.8
-20
0
20
40
60
16.6 -40
-20
TEMPERATURE (C)
0 20 40 TEMPERATURE (C)
60
80
FIGURE 8. 12V, 3V GATE DRIVE
FIGURE 9. PUMP VOLTAGE
54.5 VOLTAGE THRESHOLD (mV)
102.5 VOLTAGE THRESHOLD (mV)
54.0
12 OC Vth
102.0
12 OC VTth
53.5
101.5
3.3 OC Vth 53.0
101.0
3.3 OC Vth
52.5 -40
-20
0
20
40
60
80
100.5 -40
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 10. OC VOLTAGE THRESHOLD WITH RLIM = 5k
FIGURE 11. OC VOLTAGE THRESHOLD WITH RLIM = 10k
8
FN9104.4 October 2, 2008
ISL6161 Typical Performance Curves
(Continued)
10.2 VDD LOW TO HIGH POWER ON RESET (V)
10.0
9.8
VDD HIGH TO LOW
9.6 -40
-30 -20 -10
0
10
20
30
40
50
60
70
80
TEMPERATURE (C)
FIGURE 12. POWER-ON RESET VOLTAGE THRESHOLD
9
FN9104.4 October 2, 2008
PCI-Express Implementation of ISL6161 and ISL6118
INTERSIL ISL6161 12V, 3.3V POWER CONTROLLER INTERSIL ISL6161 12V, 3.3V POWER CONTROLLER SLOT 1 PWREN# SLOT 2 PWREN# SLOT 1 PWRGD SLOT 2 PWRGD
3.3V GATE SWITCH
+12V GATE SWITCH
3.3V GATE SWITCH
3.3V 3.3V
+12V GATE SWITCH
+12V
+12V
3.3V
3.3V
INTERSIL ISL6118 3.3VSB DUAL 3.3VAUX POWER CONTROLLER
3.3VAUX
3.3VAUX
10
12V +12V
CONTROLLER
ISL6161
SLOT 1 PRSNT
SLOT 2 PRSNT
PCI-EXPRESS SLOT 1
PCI-EXPRESS SLOT 2
SLOT 2 PWREN# SLOT 1 PWREN# SLOT 2 PWRFLT# SLOT 1 PWRFLT#
FN9104.4 October 2, 2008
ISL6161 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 5.80 0.25 0.40 14 0o MAX 1.75 0.25 0.51 0.25 8.75 4.00 6.20 0.50 1.27 8o NOTES 9 3 4 5 6 7 Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497 0.2284 0.0099 0.016 14 0o
MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574 0.2440 0.0196 0.050 8o
A1 B C D E

A1 0.10(0.004) C
e
B 0.25(0.010) M C AM BS
e H h L N
0.050 BSC
1.27 BSC
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN9104.4 October 2, 2008

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